1. Field of the Invention
This invention relates to a semiconductor device having bipolar transistors and a method for manufacturing the same, and more particularly to a Bi-CMOS device and a method of manufacturing the same.
2. Description of the Related Art
FIG. 1 is a cross sectional view showing the construction of a Bi-CMOS device having a bipolar transistor and CMOS transistors disposed therein disclosed in Japanese Patent Application No. 63-170683 filed by the Applicant of this invention. In FIG. 1, reference numeral 1 denotes a P-type substrate, 2 an N.sup.+ -buried layer, 3 a P.sup.+ -buried layer, 4 an N-type epitaxial layer, 5 a P-well region, 6 an N-well region, 7 a field oxide film, 9 an N.sup.+ -diffused layer, 13 a polysilicon layer, 14 a gate oxide film, 15 an nMOS source region having a low impurity concentration, 16 an nMOS drain region having a low impurity concentration, 17 a pMOS source region, 18 a pMOS drain region, 19 an external base region, 20 a CVD-SiO.sub.2 film, 21 an nMOS source region having a high impurity concentration, 22 an nMOS drain region having a high impurity concentration, 24 a base region, 28 a polysilicon layer serving as an emitter electrode, 30 an emitter region, 32 an interlayer film, and 36, 37 and 38 aluminum wirings. The pMOS transistor, nMOS transistor and bipolar transistor are formed on the same P-type substrate 1.
In the Bi-CMOS with the above construction, a drawback that the withstanding voltage between the emitter 30 and the collector 4 may be lowered occurs when the impurity concentration of the N-type epitaxial layer 4 acting as a collector of the bipolar transistor is high. In order to solve this drawback, it is considered to set the impurity concentration of the N-type epitaxial layer 4 lower than a predetermined impurity concentration.
FIG. 2 shows the relation between the impurity concentration of the collector and the collector-emitter withstanding voltage (open base). As shown in FIG. 2, as the impurity concentration Nc of the collector becomes lower, the collector-emitter voltage BV.sub.CEO becomes higher.
However, when the impurity concentration of the N-type epitaxial layer 4 of the bipolar transistor is lowered, current flows via a PNP parasitic transistor formed of the P-well region 5, N-type epitaxial layer 4 and base regions 24 and 19, causing a punch-through phenomenon. When the impurity concentration of the N-type epitaxial layer 4 is lowered, the resistance of the N-type epitaxial layer 4 becomes larger, making the col lector resistance larger.